MENTOR FORUM 2018

mentor forum 2018

Sheraton Hsinchu Taiwan
August 28,2018

Welcome

30多年來，半導體產業通過引入新技術、優化的性能、更精準及更多的自動化，力求應對設計和製造方面的挑戰。因應自動駕駛、人工智慧、機器學習、5G等新應用技術，一種革命性的方法必不可少。而統一、協調且可擴展的方法，包括需求管理系統、合規的設計流程和品質為核心的生產，是應對當今設計挑戰的唯一途徑，我們稱之為“EDA 4.0（電子設計自動化 4.0）”
　
Mentor, a Siemens Business——EDA電子設計自動化的全球領導者，持有提供一流解決方案的獨特地位，能協助通訊、半導體、電腦、消費電子產品、汽車電子產品、國防工業等產業的客戶加快其電子及機械產品的研發速度、提高產品品質並增加成本效益。為了協助客戶掌握最新趨勢及應用，Mentor, a Siemens Business 將於8月28日（星期二）在新竹豐邑喜來登大飯店舉辦一場技術論壇大會 Mentor Forum。除了與您分享領先的IC設計、IC封裝、汽車電子、物聯網（IoT）、功率優化等解決方案，我們也邀請來自台灣清華大學、Silicon Creations、TowerJazz、台積電（TSMC）等特別嘉賓與您分享並交流技術領域的經驗。Mentor Forum期待以技術資訊整合平台的角色，讓 IC設計及封裝領域的工程師都可在此切磋討論各自領域的發展與挑戰。
　
在今年特別設計的議程中，您可以從五種不同的產品分組挑選，或以色彩矩陣的方式參與三大熱門話題，如大型設計、車用和新技術。無論哪一種，都保證讓您滿載而歸！
　
歡迎各位業界菁英參與Mentor Forum，本活動完全免費，千萬不要錯過！

Keynote Speaker

WALDEN C. RHINES

President and Chief Executive Officer

Mentor, a Siemens business

Agenda

START	END	Track 1 Calibre	Track 2 DFT	Track 3 Functional Verification	Track 4 Emerging Methodologies	Track 5 AMS-System
09:00	10:00	Registration/ Welcome Coffee / Vendor Fair
10:00	10:10	Welcome Speech
10:10	11:00	Keynote I: Domain Specific Accelerators Drive New Startups and Next Generation Semiconductor Technology Dr. Walden Rhines, President and CEO, Mentor, A Siemens Business
11:00	11:50	Keynote II: Challenges and Opportunities for Future Semiconductor Products in the IOT Era Dr. Cheng-Wen Wu, Director of IC Design Technology Center & Tsing Hua Distinguished Chair Professor of EE
11:50	12:00	Break-out Session Introduction
12:00	13:00	Lunch / Vendor Fair
13:00	13:45	Calibre LVS: Not just Layout versus Schematic anymore	Accelerating Test Pattern Bring-up for Rapid First Silicon Debug	Low-Power IP Design – The Key is Catching it Early	The Next Big Thing in Design Driving the Next Big Thing in Verification	AMS Verification Methodology for GPUs in AI and Deep Learning Applications
13:45	14:30	Maximizing Reliability Verification Throughout TSMC Ecosystem Co-presented with TSMC	Yield Ramp on Advance Process Node	Veloce Strato Platform: Prepared for 5G Platform Deployment	HLS to the Rescue for Computer Vision and Deep Learning	What is new in AMS Verification and Solido acquisition at Mentor Graphics
14:30	14:50	Coffee Break / Vendor Fair
14:50	15:35	Ensuring Silicon Success for Leading Edge IP Design Co-presented with Silicon Creations	Hierarchy DFT on Huge Design	Veloce Emulation Platform Brings Unique Solutions to Automotive Market	7nm is Here! What does that mean for you for Calibre nmDRC, and Physical Verification as well as larger nodes	Heterogeneous High Density Advanced Packaging prototyping with Calibre verification
15:35	16:20	Verification for High Density Advanced Packaging Design (3D-IC)	Automotive Semiconductor Reshaping Test	Portable Stimulus: A New Hope	How to Significantly Improve Time to Tapeout Digital Designs with the Latest Calibre Integration	Moving Data at the Speed of Light: TowerJazz and Mentor Solutions enable Photonic ICs in an Open Foundry Silicon Photonics Process Co-presented with TowerJazz
16:20	16:30	Closing Comment / Lucky Draw

■ Large Design

■ Automotive

■ New Technology

Registration

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Keynote

WALDEN C. RHINES

President and Chief Executive Officer

Mentor, a Siemens business

Bio: Walden C. Rhines is President and Chief Executive Officer of Mentor, a Siemens business. He was previously CEO of Mentor Graphics for 23 years and Chairman of the Board for 17 years. During his tenure at Mentor, revenue nearly quadrupled and market value of the company increased 10X. Prior to joining Mentor Graphics, Dr. Rhines was Executive Vice President of Texas Instruments’ Semiconductor Group. During his 21 years at TI, he was President of the Data Systems Group and held numerous other semiconductor executive management positions. Dr. Rhines has served on the boards of Cirrus Logic, QORVO, TriQuint Semiconductor, Global Logic and as Chairman of the Electronic Design Automation Consortium (five two-year terms) and is currently a director. He is also a board member of the Semiconductor Research Corporation and First Growth Children & Family Charities. He is a Lifetime Fellow of the IEEE and has served on the Board of Trustees of Lewis and Clark College, the National Advisory Board of the University of Michigan and Industrial Committees advising Stanford University and the University of Florida. Dr. Rhines holds a Bachelor of Science degree in engineering from the University of Michigan, a Master of Science and PhD in materials science and engineering from Stanford University, a master of Business Administration from Southern Methodist University and Honorary Doctor of Technology degrees from the University of Florida and Nottingham Trent University.

Dr. Cheng-Wen Wu

Director of IC Design Technology Center &

Tsing Hua Distinguished Chair Professor of EE

Bio: Cheng-Wen Wu received the BSEE degree from National Taiwan University in 1981, and the MS and PhD degrees in ECE from UCSB in 1985 and 1987, respectively. Since 1988, he has been with the Department of EE, National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently a Tsing Hua Distinguished Chair Professor. He has served in the past at NTHU as the Director of Computer Center, Chair of EE Department, Director of IC Design Technology Center, Dean of the College of EECS, and Senior Vice President for Research. When he was on leave from NTHU in 2007, he served at ITRI as the General Director of the SOC Technology Center, and the Vice President and General Director of the Information and Communications Labs.

Dr. Wu received the Distinguished Teaching Awards from NTHU, the Outstanding Electrical Engineering Professor Award from the Chinese Institute of Electrical Engineers (CIEE), the Distinguished Research Awards from National Science Council, the Industrial Collaboration Awards from the Ministry of Education (MOE), the Academic Award from MOE, the National Endowed Chair Professorship from MOE, the EE Medal from CIEE, etc. His current interests include memory test and repair, and design and test of symbiotic IOT devices and systems. He is a Fellow of the IEEE.

Title: Challenges and Opportunities for Future Semiconductor Products in the IOT Era

Abstract: Over the past thirty years, the global semiconductor business shows an encouraging trend of growth in general, with only a few glitches that did not hinder the long-term trend. The growing trend, however, slows down in recent years with the saturating smartphone market, until late 2016 when AI suddenly gave everybody new hope. Meanwhile, the Internet-of-Things (IOT) has long been identified, or expected, as the main driving force of growth for many industries in the future. Unfortunately, so far IOT has not given a great boost to the semiconductor industry, due to limitations in global economy and energy consumption. What, then, are the specific problems and challenges to semiconductors? If IOT is going to give a boost to the stagnant semiconductor industry, what will be the key factors of its success? Is it AI? In my speech, I will try to address these issues. This speech is meant for triggering more research activities regarding establishing a sound IOT platform that allows heterogeneous integration of technologies and partners to migrate certain industries based on the notion of IOT.

Abstracts

Track 1-1

Calibre LVS: Not just Layout versus Schematic anymore
Mentor: Myron Lin, Senior Foundry Technical Lead
Everyone knows that Calibre LVS is the accepted standard when it comes to Layout versus Schematic checking. What you may not know is that by linking the physical design to the logical design, Calibre LVS enables accurate and inefficient downstream flows such as parasitic extraction and circuit simulation. This session will talk about how LVS has evolved to extract advanced BSIM parameters, offer interfaces to Mentor and 3rd party tools, and offer methodologies such as Grey/Black Box to enable efficient design flows. Additionally, we will discuss core improvements that address overall Turn-Around Time (TAT), debugging of circuit errors such as shorts and opens, and enhanced capabilities for basic Electrical Rule Checks (ERC).

Track 1-2

Maximizing Reliability Verification Throughout TSMC Ecosystem
TSMC: Maggie Chou, Technical Manager
Mentor: Yi-Ting Lee, Foundry Technical Lead
Efficient and robust IC verification is best achieved when leveraging foundry-supported rule decks focused on reliability. From IP provider to final chip assembly, this baseline establishes essential acceptance criteria for the entire design flow for automotive as well as other markets. Mentor has partnered with TSMC to present you how to best leverage the TSMC foundry-supported rule decks based upon the Calibre® PERC™ reliability verification platform. This session will address quick start hints, and various use models to help fabless chip designers be able to both run and quickly analyze the potential reliability risks within their designs.

Track 1-3

Ensuring Silicon Success for Leading Edge IP Design
Silicon Creations: Andrew Cole, VP Business Development
Mentor: Christopher Clee, Product Marketing Manager
IP design at advanced nodes require IP providers to develop circuits that are flexible enough to be used across a variety of applications and precise enough to meet tight tolerances for power, performance, and area. Silicon Creations is a leading IP provider targeting the most advanced process nodes. They have aggressive product specifications and time to market constraints. This session will introduce Silicon Creations and their product portfolio. Additionally, Silicon Creations will discuss their design challenges and how Calibre xACT helps to address their parasitic extraction requirements.

Track 1-4

Verification for High Density Advanced Packaging Design
Mentor: Yoyo Li, Foundry Technical Lead
High density advanced packages, including fan-out wafer-level packaging, silicon interposer, or die-on-die stacks, involve integration of complex components from divergent process technologies. Ensuring the designs yield and meet intended functional specs requires new techniques across the die and package design infrastructures. In this session we will present a novel approach to design, validate connectivity, and enable post-layout simulation and timing closure with minimal implications to the design flows.

Track 2-1

Accelerating Test Pattern Bring-up for Rapid First Silicon Debug
Mentor: Dragon Hsu, AE Manager
Reducing the silicon bring-up phase is critical in getting new ICs into the hands of customers. Turning chip level test failures into actionable results requires detailed knowledge about the DFT architecture as well as how test patterns are turned into a test program. In this presentation, we will demonstrate new technology for bench-top debug and characterization of ATPG patterns without the need for costly ATE time. Within the same Tessent platform that generates patterns and diagnoses failures, you can now apply tests and capture results. Learn how you can reduce the silicon bring-up cycle time with Tessent SiliconInsight for ATPG and an off-the-shelf hardware adaptor.

Track 2-2

Yield Ramp on Advance Process Node
Mentor: Manish Sharma, Development Engineering Manager
In advanced process nodes there is a significant increase in complexity of the front end layer fabrication due to use of FinFet transistors, multi-patterning etc. This results in a higher chance of systematic of yield issues in these lower metal layers inside library cells. Due to this, volume layout-aware diagnosis based analysis, which in the past has been used successfully to identify yield issues in the back end interconnect layers, is no longer sufficient. In this talk we will see how statistical analysis of volume cell-aware diagnosis results can provide a much higher resolution view into defect distributions inside cells. This allows for more targeted die picking for failure analysis, reduced FA cycle time and faster time to root cause for advanced technology nodes.

Track 2-3

Hierarchy DFT on Huge Design
Mentor: Mohammed Abdelwahid, Technical Marketing Engineer
This session is designed for engineers who use DFT tools, and want to learn more about the Tessent hierarchical DFT methodologies and techniques. We will review basic concepts of hierarchical DFT before getting into specific areas such as wrapper insertion, gray box generation, scan pattern retargeting, IJTAG and diagnosis. Special emphasis will also be placed on new advanced capabilities including architecture planning, clock control, top level integration with Test Access Mechanisms and flow automation. This session will help attendees understand the value of hierarchical DFT, what technology components are required for implementation, and how those components fit into a comprehensive hierarchical DFT flow.

Track 2-4

Automotive Semiconductor Reshaping Test
Mentor: Mohammed Abdelwahid, Technical Marketing Engineer
We are in the midst of an automotive electronics explosion. The combined move towards electric vehicles and autonomous driving is resulting in a rapid increase in both the number and complexity of electronic components integrated within a car. This rapid change is creating challenges for both device suppliers and integrators as they scramble to understand and define critical quality and reliability requirements and implementation solutions driven largely by the ISO 26262 standard. The Mentor Tessent product family offers a comprehensive set of semiconductor test solutions to address these evolving functional safety requirements. The Tessent solutions cover all parts of the chip (both digital and analog) and provide solutions for addressing both power-on as well as runtime test needs.

Track 3-1

Low-Power IP Design – The Key is Catching it Early
Mentor: Stuart Clubb, Sr. Product Marketing Manager
In multiple markets, achieving low-power is no longer a “good to have” but a “must have” trait for many IPs. For the most effective low-power design, IPs need to be “low-power qualified” early in the design cycle as power reduction techniques are most effective at the early design stage (during micro-architecting). PowerPro’s “Early Design Checks” for low-power help IP designers easily find structural and functional redundancies in the design and identify and quantify “low-effort, high return” potential power saving opportunities early in the design cycle, even when RTL may be raw and vectors may not be available. IP design teams and management can qualify their IPs for power by specifying objective criteria for these checks and optimize IPs that fail these checks. IP power can be tracked and the reduction trend may be observed; providing a complete design-for-low-power methodology.

Track 3-2

Veloce Strato Platform: Prepared for 5G Platform Deployment
Mentor: Shakeel Jeeawoody, Strategic Alliance Sr. Marketing Manager
The vision of 5G is becoming clearer as we move closer to 2020. Most experts agree that 5G will bring blazingly fast network speeds at 20 G/bps or higher and have a latency that is mere milliseconds. Not only will people be connected to each other, but so will machines, automobiles, city infrastructure, public safety and more. Looking ahead to this major transformation in cellular technology, Mentor acquired Sarokal Test Systems, a company who has been at the forefront of the 5G movement since its inception. This session will explain the rationale for the acquisition of Sarokal and describe the roadmap of planned technology. Technology that fuses the Veloce emulation platform with Sarokal’s fronthaul testing technology to accomplish early and flexible verification and validation of 5G chip sets both pre- and post-silicon to accelerate 5G deployment.

Track 3-3

Veloce Emulation Platform Brings Unique Solutions to Automotive Market
Mentor: Philip Vanness, Product Marketing Manager
Major trends such as ADAS/Autonomous driving, Connectivity and Advanced security are on the verge of revolutionizing the way automobiles are used. These trends bring significant implications for the design and verification of increasingly complex electronic systems. For instance, ADAS/autonomous driving demands much higher levels of HW/SW integration and complexity, and a huge quantity of sensor data that needs to be processed. And of course many functions are safety critical as defined within the context of ISO26262. All of this puts massive strain on current verification techniques, and requires the emergence of new equally innovative verification technologies to answer to all aspects of automotive electronics design. Join us for this session as we explore how the Veloce Emulation platform is positioned to deliver optimal verification solutions for the automotive market.

Track 3-4

Portable Stimulus: A New Hope
Mentor: Gordon Allan, Product Marketing Manager
The new Portable Stimulus Standard from Accellera provides the next leap in verification productivity for SoC verification. From a single abstract specification of test intent and coverage, tools can automate the generation of multiple target-specific test implementations for different platforms throughout the verification process, from virtual prototypes to RTL simulation, emulation, FPGA prototypes and post-silicon, freeing the verification team from the tedious and error-prone process of trying to re-implement tests in different languages. This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology. We will also show how Questa inFact, Mentor’s portable stimulus solution, will allow you to witness the power of this fully operational standard.

Track 4-1

The Next Big Thing in Design Driving the Next Big Thing in Verification
Mentor: Gordon Allan, Product Marketing Manager
Our industry has experienced remarkable breakthroughs in computing, networking, and communication technology in recent years. Yet, it is the convergence of these technologies that is driving the next big thing in innovation related to IoT and autonomous systems. And it is also driving the need for new approaches to verify today’s complex systems. In this Verification Academy session, Harry Foster shares a holistic view of the next big wave in verification.

Track 4-2

HLS to the Rescue for Computer Vision and Deep Learning
Mentor: Stuart Clubb, Sr. Product Marketing Manager
The algorithms to teach a computer to “see, understand and make decisions”, require a significant amount of parallel compute performance at the lowest possible power. HLS (High-Level Synthesis) is now finding itself in accelerated adoption for computer vision applications due to unique capabilities and market drivers. This session presents an HLS introduction, what real customers are able to achieve with it, and why it is such a good fit to accelerate delivery of high-performance, low-power hardware from rapidly changing algorithms and neural networks.

Track 4-3

7nm is Here! What does that mean for you for Calibre nmDRC, and Physical Verification as well as larger nodes
Mentor: John Ferguson, Product Marketing Director
Come learn more on how Calibre has worked with all the foundry ecosystems to ensure there are solutions in place for 7nm or whatever your next node is. Be up to date on the most recent advances in Calibre nmDRC, Multi-Patterning, Pattern Matchign and DFM.

Track 4-4

How to Significantly Improve Time to Tapeout Digital Designs with the Latest Calibre Integration
Mentor: Ming Ting, Foundry Ecosystem Relationship Manager
At advanced nodes, physical design and verification engineers sometimes have to spend days to close sign-off DRC, even when using automatic fixing tools in the P&R environment. This session will highlight how a customer, Inphi, uses Calibre RealTime Digital to dramatically reduce the turn-around time for sign-off DRC closure and speed time to tape-out.

Track 5-1

AMS Verification Methodology for GPUs in AI and Deep Learning Applications
Mentor: Sathish Balasubramanian, Sr. Product Manager
Artificial Intelligence and Deep learning based applications are the main drivers behind the current exponential increase in demand for computational power. This demand is predominantly being addressed now by GPUs instead of traditional CPUs. GPUs are high-performance, high-throughput chips which require I/O bandwidth of the order of Gbps and high-bandwidth memory interfaces. This talk will provide an overview of the AI and deep learning applications using GPUs, the added complexities on AMS verification and the methodology used to address these verification challenges in efficient and predictable ways.

Track 5-2

What is new in AMS Verification and Solido acquisition at Mentor Graphics?
Mentor: Sathish Balasubramanian, Sr. Product Manager
This session will cover the latest enhancements available from Mentor (and recently acquired Solido) to address the most complex analog/mixed-signal (AMS) circuit verification challenges. Applications range from datacenter SoCs in the latest FinFET technology to automotive ICs implemented in BCD technology. For mixed-signal SoCs implemented in the latest nanometer CMOS technologies, the Analog FastSPICE Platform (BDA acquisition) provides the world's fastest circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. For analog-centric ICs in BCD and other analog technologies, the Eldo Platform relies on over 18 years of proven sign-off customer usage offering differentiated solution for reliability verification and comprehensive circuit analysis & diagnostics. We will also provide an overview of Solido product portfolio that comprises of the variation designer and ML Char products .

Track 5-3

Heterogeneous High Density Advanced Packaging prototyping with Calibre verification
Mentor: Eddy Lu, Application Engineer
This session will discuss and demonstrate solutions to the three major challenges design teams face with heterogeneous multi-die and multi-substrate packages.
• Package Assembly Validation and Verification
• Heterogeneous Planning and Rapid Prototyping
• Physical Implementation and Signoff Leveraging Calibre

Track 5-4

Moving Data at the Speed of Light: TowerJazz and Mentor Solutions enable Photonic ICs in an Open Foundry Silicon Photonics Process
TowerJazz: Jerry Wang, Sales Director
Mentor: Terence Chen, Worldwide Foundry Alliance Manager
In this paper we present a comprehensive design and verification platform for an industry-leading open foundry Silicon Photonics process (PH18) that is targeted for optical networking, data center interconnect and sensor applications. For optical device design, non-traditional structures such as “Curved lines / edges”, “Free angled edges” and “Acute angle corners” are frequently synthesized. Typical electronic IC PDK’s do not lend themselves directly to photonics design. TowerJazz and Tanner have collaborated to resolve the unique challenges in the automation of the layout of photonics circuits. Furthermore, TowerJazz and Calibre have collaborated to develop advanced verification algorithms using the Calibre equation-based DRC (eqDRC) technology. Calibre eqDRC provides flexible rule check algorithms so that false errors arising from the peculiarity of optical circuit design can be suppressed while minimizing the risk of missing real errors with simplified screening algorithms. Real-world examples will be discussed highlighting both development and use of Mentor’s products and capabilities.